1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor wafer having formed on its surface a strained Si layer with internal two-dimensional tensile strain.
2. Description of the Related Art
As used herein, Patent Document 1 refers to
Japanese Laid-Open Patent Publication No. 9-180999 (claim 2 and paragraphs [0020], [0021] and [0031]) and
Patent Document 2
Japanese Laid-Open Patent Publication No. 11-233440 (claim 2 and paragraph [0006])
Reportedly, in order to enhance the performance of semiconductor devices employing a silicon single crystal, it is effective to increase the mobility of electrons or holes in the silicon single crystal. Specifically, the mobility of carriers is enhanced by employing a strained Si layer with internal two-dimensional tensile strain as a silicon layer where the electrons or holes flow, and therefore, based on this technique, for example, C-MOS devices capable of operating at high speed have been studied. A semiconductor wafer with a strained Si layer is manufactured by forming a relaxed SiGe layer, which has a larger lattice constant than Si, on an Si wafer through epitaxy, and forming the strained Si layer through epitaxial growth of a thin Si layer on the relaxed SiGe layer. Since the SiGe layer formed on the Si wafer has a Ge concentration of up to 30%, crystal defects such as misfit dislocation occur due to the difference in lattice constant between the Si substrate and the SiGe layer, adversely affecting the strained Si layer formed on the SiGe layer. The density of crystal defects caused by conventional manufacturing methods is in the range of approximately 1×105 to 1×107 defects/cm2. To solve this problem, some methods have been proposed, including a method employing a buffer layer with a composition ratio of Ge in SiGe being increased at a constant gentle gradient, a method employing a buffer layer with a stepwise changing Ge composition ratio, a method employing a buffer layer with a Ge composition ratio changing in a superlattice pattern, and a method employing a buffer layer with a Ge composition ratio being changed at a constant gradient by using an Si offcut wafer.
One of such methods proposed for manufacturing a semiconductor wafer with a strained Si layer while suppressing crystal defects is a semiconductor device manufacturing method including the steps of: preparing a substrate composed of an Si-oxide layer and a first Si layer, which are provided in order on an Si support, and forming a dislocation conversion layer (Ge layer) on the first Si layer through epitaxy, in which the dislocation conversion layer, when in an unstrained state, has a lattice constant different from that of unstrained Si and that of SiGe having the same composition as an SiGe layer to be grown next; forming the SiGe layer on the dislocation conversion layer through epitaxy; lattice-relaxing the SiGe layer through heat treatment; and forming a second Si layer in a strained state on the SiGe layer through epitaxy (for example, refer to Patent Document 1). According to this Patent Document 1, by employing the dislocation conversion layer such as the Ge layer, local strain is induced at and parallel to the interface between the first Si layer and the dislocation conversion layer through heat treatment, for example, at 800° C. for one hour, and when the SiGe layer is lattice-relaxed by the heat treatment, the local strain causes threading dislocation occurring in the first Si layer to be converted into glide dislocation at the interface, so that the threading dislocation does not reach the SiGe layer. Thus, according to the above publication, it is possible to obtain a semiconductor device with an SOI substrate having a high-quality strained Si layer and a thin SiGe layer underlying the Si layer. In addition, there have been disclosed semiconductor devices including: a crystal substrate; an insulating crystal thin film formed on the crystal substrate; a first crystal thin film formed on and highly lattice-matched to the insulating crystal thin film; and a second crystal thin film formed on the first crystal thin film, having a lattice constant different from that of the first crystal thin film and a thickness less than a critical thickness to induce lattice relaxation (for example, refer to Patent document 2). According to this Patent Document 2, by employing calcium fluoride and γ-alumina as materials for the insulating crystal thin film, it becomes possible to introduce sufficient strain to a semiconductor crystal thin film formed in a thickness of 100 nm or less on the insulating crystal thin film.
In both the techniques disclosed in Patent Documents 1 and 2, the strained Si layer is formed by epitaxially growing the Si layer on the SiGe layer having a larger lattice constant than Si, thereby solving two problems of inducing strain in the Si layer using a sufficiently lattice-relaxed SiGe layer, and preventing dislocation from occurring in the SiGe layer in order not to propagate the dislocation during the growth of the strained Si layer.
However, the manufacturing method disclosed in Patent Document 1 has a disadvantage in that if the heat treatment for lattice relaxation is carried out at 800° C., glide dislocation required for sufficiently relaxing the SiGe layer does not occur at the interface, resulting in unsuccessful lattice relaxation, hence insufficient strain. Note that if the heat treatment is carried out at 1000° C. or higher, the Ge layer is caused to melt, so that surface roughness progresses and crystal defects are induced. In addition, the semiconductor device disclosed in Patent Document 2 uses a specialized layer such as calcium fluoride, making it difficult to apply a conventional semiconductor manufacturing process, resulting in a high manufacturing cost, and further resulting in a lack of versatility, e.g., it is difficult to thin the device to 100 nm or less. Furthermore, the semiconductor devices with the strained Si layer as disclosed in patent documents 1 and 2 require at least two thin film growth processes, and are composed of a complicated multi-layered structure, which requires a number of processes, and therefore it is not always possible to manufacture a high-quality semiconductor wafer nor to manufacture it in a simplified manner.